A variety of techniques are used to stack packaged integrated circuits. Some methods require special packages, while other techniques stack conventional packages. In some stacks, the leads of the packaged integrated circuits are used to create a stack, while in other systems, added structures such as rails provide all or part of the interconnection between packages. In still other techniques, flexible conductors with certain characteristics are used to selectively interconnect packaged integrated circuits.
The predominant package configuration employed during the past decade has encapsulated an integrated circuit (IC) in a plastic surround typically having a rectangular configuration. The enveloped integrated circuit is connected to the application environment through leads emergent from the edge periphery of the plastic encapsulation. Such “leaded packages” have been the constituent elements most commonly employed by techniques for stacking packaged integrated circuits.
Leaded packages play an important role in electronics, but efforts to miniaturize electronic components and assemblies have driven development of technologies that preserve circuit board surface area. Because leaded packages have leads emergent from peripheral sides of the package, leaded packages occupy more than a minimal amount of circuit board surface area. Consequently, alternatives to leaded packages known as chip scale packaging or “CSP” have recently gained market share.
CSP refers generally to packages that provide connection to an integrated circuit through a set of contacts (often embodied as “bumps” or “balls”) arrayed across a major surface of the package. Instead of leads emergent from a peripheral side of the package, contacts are placed on a major surface and typically emerge from the planar bottom surface of the package.
The goal of CSP is to occupy as little area as possible and, preferably, approximately the area of the encapsulated IC. Therefore, CSP leads or contacts do not typically extend beyond the outline perimeter of the package. The absence of “leads” on package sides renders most stacking techniques devised for leaded packages inapplicable for CSP stacking.
Memory expansion is one of the many fields in which stacked module solutions provide advantages. For example, the well-known DIMM board is frequently populated with stacked modules from those such as the assignee of the present invention. This adds capacity to the board without adding sockets.
A memory expansion board such as a DIMM, for example, provides plural sites for memory IC placement (i.e., sockets) arranged along both major surfaces of a board having an array of contacts dispersed along at least one board edge. Although stacking reduces interconnect length per unit of memory, it does increase the raw number of devices on a DIMM board. Consequently, despite the reduction in interconnect length per unit of memory, signals accessing data stored in memory circuits physically placed on the DIMM board are typically presented with a higher impedance as the number of devices on the bus is increased by stacking.
What is needed, therefore, is a technique and system for stacking CSPs that provides a thermally efficient, reliable structure that performs well at higher frequencies but does not add excessive height to the stack yet allows production at reasonable cost with readily understood and managed materials and methods and allows significant reductions in loading when employed in memory expansion boards and design.